The present invention relates to a data transmission system for transmitting data via the power supply line, which controls branching terminal units connected to the power supply line, while normally surveilling conditions of such terminal units, by transmitting high frequency AC signals to the AC commercial frequency in the power supply line and internally mixing them together.
Conventionally, any existing means for transmitting and receiving a data using signals synchronized with the AC commercial frequencies via the power supply line can be easily and correctly synchronized, while it can effectively offset any adverse effect from either noise or impedance occurring synchronous with the AC commercial frequencies, and as a result, it effectively stabilizes reliability on the data transmission system.
Conversely, since the data transmitting speed is largely limited by the existing AC commercial frequencies, all the data have to be transmitted at an extremely slow speed, i.e., 1 bit per cycle, and so a long period of time is required, for example, for collectively sampling data signals from many terminal units on line by poling.
FIG. 1 shows a simplified diagram of a conventional data transmission system via the power suuply line. Central processing unit (CPU) 1 transmits the control command to the terminal units 2 via the power supply line 3 by turning switches on and off to execute any designated operation, for example, On/Off operations for the power and illumination, or it usually surveys and displays operative conditions of respective terminal units 2, for example, existing conditions of the power source, illumination, or sensors, or alternatively, it causes an alarm to be generated in case of emergency. These terminal units 2 respectively incorporate the selfselective function so that they can enter operations only when specific signals are detected.
Actually, there are three signal transmission systems most widely made available. The first is contention system, by which signal transmission can be started upon contesting available channel lines as soon as such a need for signal transmission arises. The second is a time division stationary slot allocation system, which, as shown in FIG. 2, activates the CPU 1 to output a specific code H in order to establish a system synchronization before either transmitting or receiving data 21 through 25 to and from respective terminal units 2 via the preliminarily allocated slots. The third is a polling system, which, as shown in FIG. 3, activates the CPU 1 to output signals P1, P2, and P3, each containing an address signal, while any of the terminal units 2 selected by these signals can feed back any data such as D1, D2, and D3.
In regard to the first contention system, since there is no relationship of synchronization between the CPU 1 and the terminal units 2 and between these terminal units 2 themselves, signals from these may collide with each other, causing a state of confusion to occur and the entire system to eventually malfunction. If this occurs, since a considerable time must be spent before the normal condition is restored, the CPU 1 will be obliged to stop sending any control command until the entire system is back to the normally operative condition. If such a failure occurs, quick service advantages inherent to such a transmission system will be lost eventually.
The second system, which is the time division stationary slot allocation system, also requires a long time to collect sampling data in each cycle if a large number of terminal units 2 are employed, since the CPU 1 will also be obliged to stop sending the control command until the next data are completely collected.
Conversely, the third system which is the polling system can collect the sampling data within a very short while in each cycle without causing the CPU 1 to stop sending the control command without any waste of time.
On the other hand, if any change should take place in the status of these terminal units 2 immediately after the polling system has collected sampling data, such a change cannot be read by the CPU 1 until the sampling data has been collected from all the remaining terminal units 2. It requires a relatively long duration compared to other conventional systems.